1. Field of the Invention
The present invention relates to a semiconductor device having a gate electrode consisting of a plurality of layers, particularly to a semiconductor device with improved gate electrode arrangement and improved impurity concentration of the diffusion layer.
2. Description of the Related Art
FIG. 8 shows the arrangement of a conventional EPROM having a gate electrode consisting of two layers. As seen from the drawing, the length of a control gate electrode 4 is about 1.3 times the length of the longer side of a single floating gate electrode 3 and about 4 times the length of the shorter side of the single floating gate electrode 3 in each unit cell 5. Also, the width of the control gate electrode 4 is equal to the length of the shorter side of the single floating gate electrode 3.
The particular construction described above causes the wiring resistance of the control gate electrode 4 not to be negligible because of the recent trend toward miniaturization of the width of the control gate electrode, i.e., the width of the polysilicon layer included in the gate. As a result, it is difficult to increase the capacity of the EPROM and to operate the EPROM at high speed. Several measures are being proposed in order to overcome these difficulties. For example, it is proposed to use a silicide material for forming the control gate electrode 4. However, the use of a silicide material fails to provide a satisfactory solution to the problem as, for example, the use of the silicide material makes it difficult to provide a sufficient margin in fine processing and gives rise to breakage of the wiring at the stepped portion.
What should also be noted is that the single cell 5 includes half of a drain contact hole 1. Thus, in determining the cell size, it is necessary to secure in advance a predetermined region, which is defined by the masking step, for each of the contact hole 1 and an element isolating region 2 and to secure an allowance for the deviation. It is also necessary to secure in advance a predetermined region, which is defined by the masking step, for each of the contact hole 1 and the floating gate electrode 3 and to secure an allowance for that deviation as well. It follows that the prior art shown in FIG. 8 leaves room for further improvement with respect to miniaturization of the device and enlargement of the memory capacity.
FIG. 9 shows another example of the prior art relating to the cell arrangement proposed for increasing the memory capacity. This prior art comprises a source diffusion layer, a drain diffusion layer, a floating gate electrode formed on a channel region between the source diffusion layer and the drain diffusion layer, and a control gate electrode formed on the floating gate electrode with an insulating layer interposed therebetween. The floating gate electrode is in an electrically floating state. It should be noted that the source diffusion layer and the drain diffusion layer are formed in parallel in the width direction of the floating gate electrode. Also, the control gate electrode is formed in parallel with the channel direction of the floating gate electrode, i.e., the current flow direction. Further, the wiring of the control gate electrode extends so as to cross the source diffusion layer and the drain diffusion layer.
In the prior art shown in FIG. 9, the diffusion layers arranged in parallel are decoded in accordance with the position of a selecting cell 8 so as to designate a drain (High voltage) 6 and a source (0V) 7. When information is written, the diffusion layers having the selecting cell 8 interposed therebetween are designated as the drain 6 and the source 7. In the adjacent cell sharing the drain 6, the diffusion layer 9 corresponding to the source is set as an open, so as to prevent an unintentional writing. Even if the diffusion layer 9 is set as the open, the diffusion layer has a large capacitance and, thus, a charging current flows to charge the diffusion layer until the potential of the diffusion layer becomes equal to that of the adjacent diffusion layer. The flowing time of the charging current is increased along with the increase in the element density. What should be noted is that channel hot electrons generated near the drain during the flow of the charging current are injected into the floating gate electrode, resulting in an unintentional writing and, thus, in an erroneous operation of the device.